In the development and fabrication of rather complex integrated circuits, considerable time, effort and other development resources are expended while progressing through a sequence of several necessary and distinct steps. A logic circuit design is developed in an initial step on an appropriate computer aided design (CAD) system usually in a graphical representation. Next, a simulation step is used to verify the correct functionality. Typically, several iterations between these first two steps are required to obtain the desired functionality. Upon obtaining the desired functionality, a physical representation, or design layout, is made providing the exact locations of all the polygons forming the respective areas that the transistors and resistors occupy. Depending on the circuit complexity, the entire circuit may be re-simulated with additional information based on the design layout. For example, the layout resistance and capacitance are typically required to predict the level of performance in high speed integrated circuits. At this point, the physical or hardware processing begins with the generation of masks in accordance with the design layout and their use in diffusions, and patterning of various layers in the actual fabrication process of producing the physical integrated circuit.
For a completely customized circuit wherein none of the circuit elements in the design layout have been prearranged, the designer of an integrated circuit may work at the transistor level representation which includes the transistors and resistors and their circuit interconnection. For the design of application specific integrated circuits (ASIC's), the design is simplified because the ASIC vendor supplies a set of circuit building blocks, called macrocells or macros. To achieve the desired functionality for an integrated circuit, these macros are located on a common chip and are connected together by conductive paths. Thus, the circuit designer is no longer burdened by the details of the transistor level representation. For the simulation, the circuit designer is provided a complete set of macro logic simulation models. A new and improved process for efficiently developing the basis for logic simulation models will be described. As mentioned, the logic simulation models serve as a valuable tool for facilitating the verification of the correct functionality of integrated circuits based on the macros.
The critical interim step between the transistor netlist and a logic simulation model is logic extraction. Logic simulation models fall into two classes. One class is to develop behavioral models which is a black box approach emulating the overall function. The other class is to develop structural models including logic gates patterned after the circuit representation of the transistor netlist. The latter class is more suitable for developing a logic simulation model automatically.
Conventional logic extraction is typically provided by two ways. The first way is to do so manually by analyzing the circuit representation of the transistor netlist to determine the equivalent logic level representation of the integrated circuit. The obvious disadvantages of the manual method are that it is time consuming and prone to error. Secondly, one could use a computer method based on a computer program for extracting the logic netlist but the primary purpose for such conventional methods of logic extraction is logic verification. In logic verification, it is necessary to extract an equivalent logic circuit (formed of logic gates such as OR, NOR, AND NAND gates) from the transistor netlist (representing transistors, resistors and interconnections, etc.). The result of the logic extraction can then be compared against the intended logic design to verify that the representation of a physical implementation provides the desired logical function. The requirements of an extracted logic netlist used for logic verification, and an extracted logic netlist for logic simulation have several fundamental differences which fail to satisfy three concurrent requirements.
The first of the three requirements of a new computerized tool is that it must be able to extract the logic netlist from emitter coupled logic (ECL) transistor netlists or current mode logic (CML) transistor netlists. Secondly, the extracted logic must be created so pin-to-pin timing delays are assignable to the logic elements. Finally, the extracted logic must be suitable to serve as a basis for a suitable interface for any one of a number of generally used logic simulators.